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수평: Nhân viên chính thức
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작업 내용
Available time:
- From April 2021
Description:
- Using Verilog HDL language to design Digital IC
- Using SystemVerilog language and UVM Methodology to design VIP (Verification IP), build simulation environment and do verification tasks for IP/SOC
Target Candidates:
3rd year or 4th year university students rank fair and above, in related majors including:
- Electronics
- Telecoms
- Automation
- Computer Engineering
- Computer Science
- Information Technology
- Mechatronics
- Physics – Electronics
- Physics – Computer Science
- Maths – Computer Science.
Prefer to have good algorithm and good knowledge on Logic Design Circuit
Understanding on Hardware Architecture
Good English skills in verbal, writing, speaking
Benefits:
- Be guided during the internship duration
- Practice in a professional working environment and acquainted with latestIC Design Technology
- Receive monthly allowance
- Be offered priority in recruitment
- Be supported on internship confirmation for your report
무료 후보 신청 클릭
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